1. Field of the Invention
The present invention relates to a processor-to-processor interfacing technique for a data processing system which is equipped with a processor, such as a vector processor, as well as a central processor unit (CPU), and more particularly to an address translation system using address information transferred from the CPU to the vector processor.
2. Specification
In FIG. 1, there is shown a data processing system equipped with more than one processor. This data processing system comprises a central processing unit (hereinafter abbreviated to CPU) 1, a processor 2, such as a vector processor unit (VPU) for performing arithmetic operations on vectors, and a memory unit 3, which are interconnected by a data bus (DBUS) 4, an address bus (ABUS) 5, and a control bus (CBUS) 6.
In such a data processing system, an internal interface 7 of the processor 2 accepts address index information sent from the CPU 1 over the address bus 5 and translates it to an internal address of the processor 2 for subsequent processing, for example for use in vector operations.
The problem with the address translation by the interface 7 is the difficulty of control because index data, which are sent from the CPU independently of the timing of address translation, must be translated to addresses in the order in which they are received.
Next, suppose that the processor 2 in FIG. 1 adopts an address translation method using a translation lookaside buffer (TLB). In recent years, a number of vector processor LSIs (large-scale integrated circuits) have been developed, each of which is equipped with a cache or a translation lookaside buffer in order to speed up processing.
Such processors have a problem of data agreement assurance for contents of the cache or the translation lookaside buffer. As for the cache, since an entry consists of a physical address and data and comparison between physical addresses is easy, the problem of data assurance can be solved by monitoring the system bus to detect rewriting of data corresponding to an entry in the cache and making the corresponding entry invalid upon detecting the rewriting.
However, regarding the translation lookaside buffer, since only pairs of logical and physical addresses are entered into the buffer and the address assigned to the buffer itself is not held, the data assurance problem cannot be solved in the same way as with the cache.
Thus, the processors are required to be equipped with a TLB control circuit that can make entries in the TLB invalid as necessary.
Each entry in a conventional TLB is provided with a V flag storage unit such as shown in FIG. 2 to indicate whether it is valid or invalid. The V flag storage unit comprises a V flag register 8 for storing a V flag, an inverter 9 supplied with a signal FF indicating that the physical address for the entry is to be updated when its priority has been decreased to the lowest and the TLB misses, and a NOR gate 10 supplied with the output of the inverter 9 and an address space switching signal, i.e., a signal indicating that the contents of an external RAM managed by the operating system (OS) have been rewritten, which is supplied by the OS. The output of the NOR gate is connected to the V flag register 8.
The V flag register 8 is reset by a system reset signal from the CPU 1 end set by a state signal EE output from a bus unit which controls the transfer of data to or from the data bus 4 within the vector processor unit 2. The state signal EE is a signal indicating TLB updating cycles, which is one of the signals produced by the bus unit and indicates internal states of the vector processor unit.
Of the above signals, the address space switching signal and the signals FF and EE are all "1" when they are active. The address space switching signal is common to all the entries in the TLB, while the signals FF and EE are associated with single entry having a one-to-one correspondence with the V flag register 8. For example, when the signal FF indicating a TLB miss is input and then the contents of the corresponding entry are updated, the V flag is set to one.
A flag value of 1 in the V flag register 8 indicates that the corresponding TLB entry is valid, while a flag value of 0 indicates that it is invalid.
In the above arrangement, when the address space switching signal becomes active to change the address space, a 1 input is applied to one of the inputs of the NOR gate 10, causing a 0 to be written into the V flag register 8. When 0s are written into all the V flag registers 8, all the TLB entries are made invalid.
Heretofore, the TLB is configured such that the flag registers indicating priorities of the TLB entries, for example, the contents of LRU flag registers to be described later, when reset, indicate a fixed order of priority. This is in order to keep a fixed order of priority even if the flag registers indicating priorities of the TLB entries are cleared on reset.
In a general system configuration, a numeric arithmetic processor connected to the CPU works by coprocessor/slave access in response to address/data from the CPU. Further, a processor that is also specialized for graphic processing may occupy a data bus and work as a bus master.
While the processor acts as a bus slave, it is necessary to invalidate all the entries in the TLB when the installed RAM with the TLB (page table base) is subjected to a write.
Further, in order to invalidate the entry, it is necessary to provide dedicated hardware, thereby making a circuit construction complicated. The conventional processor is structured such that a flag bit register designating a priority of respective entries in the TLB represent a predetermined sequence of the priority when the entries are reset. Therefore respective entries including the flag bit register can not be used for the other purpose even if they are reset, thereby failing to utilize the hardware resource efficiently.